Electronics and Communication Engineering
EC 1401 – VLSI DESIGN
(Common to B.E. part time) sixth Semester Regulation 2005)
Answer all questions
PART A – (10*2=20marks)
1. What are the advantages of SOI CMOS process?
2. Distinguish electrically alterable and non-electrically alterable ROM.
3. Compare nMOS and pMOS.
4. Compare enhancement and depletion mode devices.
5. What is meant by continuous assignment statement in Verilog HDL?
6. What is a task in Verilog?
7. Give the application of PLA.
8. What is meant by a transmission gate?
9. What is the aim of adhoc test techniques?
10. Distinguish functionality test and manufacturing test.
PART B – (5*16=80 marks)
11. (a) (i) Draw and explain the n-well process.
(ii) Explain the twin tub process with a neat diagram.
OR
(b) (i) Discuss the origin of latch up problems in CMOS circuits with necessary diagrams. Explain the remedial measures.
(ii) Draw and explain briefly the n-well CMOS design rules.
12. (a) (i) Derive expressions for the drain to source current in the nonsaturated and saturated regions of operation of an nMOS transistor.
(ii) Define and derive the transconductance of nMOS transistor.
OR
(b) (i) Discuss the small signal model of an nMOS transistor.
(ii) Explain the CMOS inverter DC characteristics.
13. (a) (i) Give a verilog structural gate level description of a bit comparator.
(ii) Give a brief account of timing control and delay in verilog.
OR
(b) (i) Give a verilog structural gate level description of a ripple carry adder.
(ii) Write a brief note on the conditional statements available in verilog.
14. (a) (i) Compare the different types of ASICs.
(ii) Discuss the operation of a CMOS latch.
OR
(b) Explain the ASIC design flow with a neat diagram. Enumerate clearly the different steps involved.
15. (a) Explain the chip level test techniques.
OR
(b) Explain the system level test techniques.
EC 1401 – VLSI DESIGN
(Common to B.E. part time) sixth Semester Regulation 2005)
Answer all questions
PART A – (10*2=20marks)
1. What are the advantages of SOI CMOS process?
2. Distinguish electrically alterable and non-electrically alterable ROM.
3. Compare nMOS and pMOS.
4. Compare enhancement and depletion mode devices.
5. What is meant by continuous assignment statement in Verilog HDL?
6. What is a task in Verilog?
7. Give the application of PLA.
8. What is meant by a transmission gate?
9. What is the aim of adhoc test techniques?
10. Distinguish functionality test and manufacturing test.
PART B – (5*16=80 marks)
11. (a) (i) Draw and explain the n-well process.
(ii) Explain the twin tub process with a neat diagram.
OR
(b) (i) Discuss the origin of latch up problems in CMOS circuits with necessary diagrams. Explain the remedial measures.
(ii) Draw and explain briefly the n-well CMOS design rules.
12. (a) (i) Derive expressions for the drain to source current in the nonsaturated and saturated regions of operation of an nMOS transistor.
(ii) Define and derive the transconductance of nMOS transistor.
OR
(b) (i) Discuss the small signal model of an nMOS transistor.
(ii) Explain the CMOS inverter DC characteristics.
13. (a) (i) Give a verilog structural gate level description of a bit comparator.
(ii) Give a brief account of timing control and delay in verilog.
OR
(b) (i) Give a verilog structural gate level description of a ripple carry adder.
(ii) Write a brief note on the conditional statements available in verilog.
14. (a) (i) Compare the different types of ASICs.
(ii) Discuss the operation of a CMOS latch.
OR
(b) Explain the ASIC design flow with a neat diagram. Enumerate clearly the different steps involved.
15. (a) Explain the chip level test techniques.
OR
(b) Explain the system level test techniques.
